This application claims priority from Korean Priority Document No. 2001-39330, filed on Jul. 2, 2001 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which is capable of adjusting the number of banks and a method for adjusting the number of banks.
2. Description of the Related Art
In most cases, the time taken to access data in dynamic access random memories (DRAMs) can be reduced by increasing the number of banks including memory blocks and thus decreasing losses in row active time. However, the increase in the number of banks decreases the efficiency of repairing defective rows in each of the banks.
FIG. 1 is a diagram illustrating a conventional semiconductor memory device using a memory block as one bank. Referring to FIG. 1, a semiconductor memory device 10 includes 2N (where N is a natural number) banks 1 through 4, and the banks 1 through 4 include normal memory cell blocks 3, 9, 15, and 21, respectively, and redundant memory cell blocks 5, 11, 17, and 23, respectively.
A method for replacing a defective cell in the normal memory cell block 3 with a normal cell in the redundant memory cell block 5 will be described with reference to FIG. 1.
The redundant cell block 5 may be set to substitute for a plurality of defective cells. However, the redundant cell block 5 is supposed to substitute for only one defective cell in the following.
If the bank 1 is activated, the other banks 3 and 4 are activated except the bank 2. In this case, sense amplifiers 1 and 7 operate normally. However, since the bank 2 is inactive, in other words, since the bank 2 is precharged, the bank 2 cannot use the sense amplifier 7.
Accordingly, if two or more defective rows are generated in the bank 1, it is impossible to replace the defective rows with redundant rows in the conventional memory device having such a structure shown in FIG. 1.
FIG. 2 is a diagram illustrating a conventional semiconductor memory device using two memory blocks as one bank. Referring to FIG. 2, a semiconductor memory device 20 includes N (where N is a natural number) banks 11 and 21, and the bank 11 includes two normal memory cell blocks 33 and 39 and two redundant memory cell blocks 35 and 41.
A method for repairing two defective rows in the normal memory cell block will be described with reference to FIG. 2. If the bank 11 is activated, sense amplifiers 31, 37, and 43 operate normally. Thus, if two defective rows are generated in the bank 11, the two defective rows are repaired by using the redundant cell block 35 and the redundant cell block 41.
FIG. 3 is a diagram illustrating the translation of bank selection addresses into row addresses in the case of transforming a semiconductor memory device including 32 banks into a semiconductor memory device including 16 banks. Specifically, FIG. 3 shows the differences in bank selection addresses and row addresses between a semiconductor memory device including 32 banks and a semiconductor memory device including 16 banks, with an arrow to indicate the transformation.
A semiconductor memory device including 2N banks needs N bank selection addresses for selecting each of the 2N banks. Accordingly, in the case of a semiconductor memory device including 32 banks, each bank selection address BADR less than i greater than  (where i is a natural number between 0 and 4) for selecting the 32 banks is comprised of 5 bits. On the other hand, in the case of a semiconductor memory device including 16 banks, each bank selection address BADR less than i greater than  (where i is a natural number between 0 and 3) for selecting the 16 banks is comprised of 4-bit addresses.
For the case of either 16 or 32 banks, there is a row address made from n+1 bits. These bits are labeled row addresses RADR less than i greater than  (where i is a natural number between 0 and n).
In addition, there is a bank address. For the general case of 32 banks, the bank address has five bits BADR less than 0 greater than , BADR less than 1 greater than , BADR less than 2 greater than , BADR less than 3 greater than , BADR less than 4 greater than . For the general case of 16 banks, however, the bank address has only four bits BADR less than 0 greater than , BADR less than 1 greater than , BADR less than 2 greater than , BADR less than 3 greater than . There will be no need for bit BADR less than 4 greater than .
In the particular case, however, where there is a conversion from 32 banks to 16 banks, there will be one less bank bit, but one more row address bit. More particularly, bit BADR less than 4 greater than , which is the most significant bit, is used as a translation row address RADR less than n+1 greater than  bit. Nevertheless, the total number of bits remains the same.
Referring back to FIG. 2, the bank 11 is selected by the bank selection address BADR less than i greater than  (where i is a natural number between 0 and 3), and the normal memory cell block 33 or 39 is selected by the translation row address RADR less than n+1 greater than . In other words, the translation row address RADR less than n+1 greater than  is used to select one out of two normal memory cell blocks constituting one bank.
A limitation of the prior art is that banks cannot be integrated easily, to exploit the redundancy. That is because semiconductor memory devices including 32 banks and semiconductor memory devices including 16 banks must be integrated in different chips. Such chips, which are designed as different integrated circuits, must be separately tested using different repairing methods. Accordingly, different manufacturing processes and testing processes are required for individual products, which makes it hard to reconfigure the blocks of a device from 32 banks to 16 banks. This lowers the productivity in a manufacturing process.
To solve the above-described problems, it is an object of the present invention to provide a semiconductor memory device which is capable of adjusting the number of banks using blocks designed on the same chip and a method for adjusting the number of banks using blocks designed on the same chip.
Accordingly, to achieve the above object, there is provided a semiconductor memory device including memory blocks having a plurality of normal memory cells and a plurality of redundant memory cells for repairing a defective normal memory cell according to a first embodiment of the present invention. The semiconductor memory device includes a switching circuit, a control circuit, and a redundancy circuit.
The switching circuit selectively transmits a first address or a second address in response to a control signal. The control circuit selectively activates 2N banks in response to Nxe2x88x921 bank selection addresses and the first address or selectively activates 2Nxe2x88x921 banks in response to the Nxe2x88x921 bank selection addresses (N is a natural number).
The redundant circuit controls the repair of the defective normal memory cells. Here, each of the 2N banks comprises one memory block, each of the 2Nxe2x88x921 banks comprises 2 memory blocks, each of which is selectively activated in response to the second address, and the defective normal memory cells are repaired in an activated bank in response to an output signal of the redundant circuit.
To achieve the above object, there is provided a semiconductor memory device including memory blocks having a plurality of normal memory cells and a plurality of redundant memory cells for repairing defective normal memory cells according to a second embodiment of the present invention. The semiconductor memory device includes a switching circuit, a control circuit, and a redundant circuit.
The switching circuit selectively transmits a first address or a second address in response to a control signal. The control circuit selectively activates 2N banks in response to Nxe2x88x922 bank selection addresses and the first address or selectively activates 2Nxe2x88x922 banks in response to the Nxe2x88x921 bank selection addresses (N is a natural number).
The redundant circuit controls repair of the defective normal memory cells. Here, each of the 2N banks comprises one memory block, each of the 2Nxe2x88x922 banks comprises 4 memory blocks, each of which is selectively activated in response to the second address, and the defective normal memory cells are repaired in an activated bank in response to an output signal of the redundant circuit.
Preferably, the first address and the second address are separately input via different input circuits and the first address is the same as the second address.
The redundant circuit includes a first fuse block, a second fuse block, and a logic circuit.
The first fuse block includes a plurality of fuses which are selectively cut in response to the second address in accordance with the memory cell block including the defective normal memory cell. The second fuse block includes a plurality of fuses which are selectively cut in response to addresses for selecting the defective normal memory cell in accordance with the rows of the defective normal memory cell.
The logic circuit performs a logic operation on the output signals of the first and second fuse blocks. Preferably, the output signal of the first fuse block is activated, the defective normal memory cell can be repaired by a memory block not-selected by the second address in the same bank as the memory block selected by the second address.
To achieve the above object, there is provided a method for adjusting the number of banks of a semiconductor memory device from 2N (where N is a natural number) into 2Nxe2x88x921 in response to a control signal according to a first embodiment of the present invention, the method including generating the control signal for transmitting a first address or a second address, selectively activating the 2N banks in response to Nxe2x88x921 bank selection addresses and the first address or selectively activating the 2Nxe2x88x921 banks in response to the Nxe2x88x921 bank selection addresses, and repairing defective normal memory cells in response to the second address.
Here, each of the 2N banks comprises K (where K is a natural number) memory cell blocks each including a plurality of normal memory cells and redundant memory cells used to repair the defective normal memory cells, each of the 2Nxe2x88x921 banks comprises 2K memory blocks, each of which is selectively activated in response to the second address, and the defective normal memory cells are repaired in an activated bank.
To achieve the above object, there is provided a method for adjusting the number of banks of a semiconductor memory device from 2N (where N is a natural number) into 2Nxe2x88x922 in response to a control signal according to a second embodiment of the present invention, the method including generating the control signal for transmitting a first address or a second address, selectively activating the 2N banks in response to Nxe2x88x922 bank selection addresses and the first address or selectively activating the 2Nxe2x88x922 banks in response to the Nxe2x88x922 bank selection addresses, and repairing defective normal memory cells in response to the second address. Here, each of the 2N banks comprises K (where K is a natural number) memory cell blocks each including a plurality of normal memory cells and redundant memory cells used to repair the defective normal memory cells, each of the 2Nxe2x88x922 banks comprises 4K memory blocks, each of which is selectively activated in response to the second address, and the defective normal memory cells are repaired in an activated bank.